Part I: The Growth of FPGA Engineers
The first stage: Getting Started -> Proficient in overcoming psychological fears - The code can be compiled and passed - The download program will not burn the circuit board and establish the mindset - "After not knowing what's easy to learn," it is "Huaishan Road since ancient times."
Never used is "Language gradually want to charming eyes
Stage 2: Improve -> Mastering EDA tools - From perceptual knowledge to rational knowledge - Stand out from the perspective of EDA tools Understanding the significance of various processes in the EDA tool flow of the FPGA development process, input and output of various stages EDA tool output report: Infor and warning HDL Languages ​​- Accumulation Design Patterns - Cross Clock Domain Processing Circuits - Finite State Machine Circuits - Field Specific Data Path Circuits - On-Chip Bus FPGA Chips - From Logical to Physical Features
– Get timing analysis and constraints – Understand the RTL view and Technology view Stage 3: Practitioner -> Expertise to understand your chip from product requirements – Understand the relationship between the underlying structure of the FPGA and the application within the chip – Off-chip FPGA Design and debug of peripheral support circuits and high-speed interface FPGAs and software interfaces Make your product – company business – project process – domain knowledge
Personal Growth + Successful Projects Give a few advices to just-in-time FPGA engineers - Value your first job to learn from work, grow your work log in your work, write blogs - FPGA engineers learn software, learn " Do not synthesize statements "glue" between data analysis and visualization tools - use Linux OS scripts
Free tool open source spirit
Part II: Agile Practices in FPGA Development FPGA development is inherently agile – as opposed to chip development: flexible + fast = agile
Can be updated at any time – Shorter iterations can be verified on the board – Faster feedback speeds The idea of ​​agile development needs to combine the features of the FPGA – Relative to software development: higher commissioning costs for board commissioning – The need for simulation verification is far from the real world More recent – ​​The need to develop verification and debugging tools » Validation and debugging tools are not part of the final product » Development tools, accumulation tools, rational reuse Reliable simulation of chip or software development is not desirable Case sharing case 1: Using Virtual JTAG Accelerate board verification
– Question 1: The simulation model of the external chip is missing. – Solution 1: Use VJ to virtualize a “serial console†and send “write†and “read†commands to the external chip through the interface logic layer. Verify the interface logic layer and accumulate scripts that operate external chips. Through this interface, the control circuit that needs to be realized by the state machine in the final product is temporarily replaced with a script that can be implemented with PC software; the hardware debugging on the FPGA is converted into PC-side software debugging, and the debugging process is accelerated. – Agile thinking: The risks in the project are solved in the early iterations.
– Question 2: External device behavior is complex, test vector coverage is insufficient, and simulation speed is slow. – Solution 2: Design a real-world behavior capture module with VJ to enrich test vectors. Using VJ virtual unrealized key logic modules, board testing and debugging. – Agile thinking: Rethinking and reviewing, discovering development bottlenecks, and continuously improving methods and tools. Early integration, early testing. Case Two: Introducing Regression Testing and Continuous Construction in FPGA Development
– Problem 1: The driver layer (C) of the software and the interface layer (V) of the FPGA need to test and debug the FPGA. Regression testing is required to guarantee the quality of continuous development. Solution 1: Connect the C and Verilog with the SystemVerilog DPI. Use the CppUtest test framework to build the FPGA. Regression Test Environment - Agile Ideas: Regression Testing
– Question 2: Quality Assurance for Codes in Multiplayer Collaborative Development FPGAs need to be built automatically to achieve timely release – Solution 2: Automate project compilation and simulation with Tcl scripts Hudson CI is used to automate multiple simulations and build projects. Health Report - Agile Ideas: Daily Build
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