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1 IntroductionWith the advancement of digital transmission technology and image processing technology, TV technology is gradually transitioning from SDTV (Standard Definition TV) to HDTV (High Definition TV). High-definition digital TV meets the needs of high-quality digital multimedia playback and high-performance network information terminals, and has broad market prospects. Its implementation based on embedded system technology has also become a new hot spot in the embedded field [1-2].
HDTV refers to high-definition television systems that play more than 720p or 1080i (i means interlaced, p means progressive). At present, the playback quality of standard definition is 480i, and the highest quality of DVD can reach 480p, which is the standard of 720x480 progressive display. It can be seen that HDTV is much clearer than the clearest DVD. The US HD standard has two main formats, 1280×720p/60Hz and 1920×1080i/60Hz, and Europe supports 1920×1080i/50Hz.
The standards for digital TV mainly include ATSC in the United States and DVB in Europe. Both of the source codes are MPEG2, and the channel coding and modulation methods are different. ATSC is for terrestrial broadcasting; DVB is classified into satellite (DVB-S), cable (DVB-C) and terrestrial (DVB-T).
HDTV currently on the market
DVB-T is convenient to receive and widely used. This paper will present a design of high-definition DVB-T digital TV based on multi-embedded processor. The DVB-T digital signal receiving module is built in the analog HDTV, and the HDTV module is implemented. The two-machine communication between the DVB-T module processors synchronizes the processing tasks and eventually combines into a complete digital HDTV system. In order to combine two independent modules, the article proposes a method to realize a single system image of the system, providing a single user interface through a single system image, a single display interface, and a single data maintenance, so that the user feels like The system is running.
2 system hardware structure
2.1 DVB-T module
The DVB-T receiver module is based on ST's HD set-top box decoder chip Sti7710[4]. It consists of a 32-bit RISC CPU ST20 and an MPEG2 A/V decoder. The A/V decoder is MP@HL-compliant and supports 1280×720p or 1920 × 1080i HD resolution output, its system hardware block diagram and signal flow shown in Figure 1. The DVB-T module is divided into three parts: front-end receive demodulation, A/V decoding, and A/V output.
The front-end receive demodulation consists of Tuner and demodulator. The terrestrial transmitted DVB-T digital TV signal is received by Tuner, and Tuner transmits the intermediate frequency signal to the QAM demodulator. The demodulator uses the ST chip STV0370 to demodulate the COFDM modulated signal and solve the MPEG TS stream. The TS stream is input to the MPEG2 A/V decoding section by inputting the Sti7710 in parallel or serially.
The MPEG2 A/V decoder firstly processes the TS stream, extracts the MPEG2 compressed audio and video data after demultiplexing, decodes the image, and adds the OSD display to output in analog and digital audio and video. The A/V output has multiple modes of analog and digital. The analog video is output in RGB, YPbPr, etc. Digital video can be output through HDMI encoding and DVI interface [5-7].
2.2 HDTV module
Based on Trident's analog HD solution, the HDTV module implements a high-definition TV that receives analog TV signals. Its system block diagram is shown in Figure 1.
The module supports analog video input such as RGB, YPbPr, CVBS and HDMI digital video input, and will process the image accordingly and superimpose its own OSD system. The processor consists of two parts, one is a 16-bit M16C/62 series MCU, which is responsible for executing the TV main control program and controlling the operation of the TV system. The other is the image processor SVP-EX52, which processes the input under the control of the MCU. The image data is output to the screen display. The main functions of the image processor are as follows: one is to convert the input interlaced image into a progressive image, and the other is to convert the input image of 24 Hz, 30 Hz and other frequency below 60 Hz into 60 Hz, and the third is Adjust the resolution and shape of the image and refill the pixel matrix so that the image can be scaled and processed as needed.
The amount of data of the high-definition signal is very large. Taking 1280×720p as an example, the amount of image data that needs to be output to the display screen per second is 1280×720×24×60 bits, which is equal to 1.327 Gbit, so the transmission rate requirement is very high. LVDS, that is, low-voltage differential signal technology achieves a transmission rate of several Gbits, which can meet the needs, so the high-definition video signal output by the image processor needs to be modulated into an LVDS signal and transmitted to a large-sized LCD liquid crystal screen or a PDP plasma screen.
Figure 1 system hardware structure
2.3 module interface
The audio and video of the two modules are connected through the HDMI interface. HDMI (High-Definition Multimedia Interface) is a new audio and video interface technology used in the field of high-definition multimedia. It has many advantages and is reflected in the following aspects:
1HDMI can transmit all digital audio and video data without compression, without D/A and A/D conversion twice, so the transmission has no loss and the best quality.
2 HDMI transmission bandwidth up to 5Gbps, currently only uses 2.5Gbps, can meet the transmission requirements of 720p, 1080i and other resolution video signals.
3 has higher anti-interference ability than analog video transmission.
4 easy to connect, easy to use. Audio and video connections and simple data transfer are possible with just one cable.
5 provides HDCP (High-bandwidth Digital Content Protection) technology to protect the copyright of media transmitted through the interface.
The UART interface is a common communication interface in embedded systems. Two embedded CPUs, Sti7710 and M16C/62 support UART interface, so it exchanges commands and data to realize task synchronization and data exchange between two CPUs. The system image provides underlying support.
3 single system image
3.1 System Analysis
For dual-processor digital TV systems, a single system image refers to a single U
The digital TV UI mainly includes remote control operation and OSD display, system menu and the like. The TV and the external set-top box are separately controlled by two remote controllers, each of which has a separate set of OSD and system menus, so the remote controller and the OSD and system menus need to be unified.
Digital TV receives data broadcasts as information terminals, maintains a simple embedded database, and the database is maintained in the DVB module and is updated in real time. Information services such as EPG (Electronic Program Navigation), Teletext (Subtext), Subtitle (Subtitle), and MHEG (Hypermedia) are provided on the basis of this database. Users can easily manage program listings and browse network information through this database [8-9].
The OSD display of the two systems and the system menu should be integrated into one of the modules as a system. HDTV is a display device. The DVB OSD and video are superimposed together as an image to the HDTV. The HDTV superimposes its own OSD on it and transmits it to the screen display. So the OSD of the entire system should be integrated on the HDTV module. The DVB module no longer generates the OSD, nor responds to the remote control. It only responds to the menu commands sent by the HDTV through the serial communication interface, and transmits the results to be displayed to the OSD display of the HDTV through the serial communication interface.
The access interfaces of data services such as EPG, Teletext, Subtitle, and MHEG are also given on the menu interface of HDTV, but due to their relatively large amount of data, the non-volatile memory of the HDTV module is relatively small, so it cannot be moved to the HDTV system. Stored, still stored in the DVB module with relatively large memory space. When the system needs to display these data, the HDTV module sends a data request to the DVB module, and the DVB module transmits the data to the OSD display of the HDTV, and the HDTV module does not need to save the data.
3.2 Dual Processor Communication Protocol
The TV module processor works in parallel with the DVB module processor. To work together, the two need to pass commands, synchronize status, and exchange data. Communication and operation between the two processors is accomplished through the UART interface. According to the application requirements, the protocol consists of a physical connection layer, a link driver layer, a transport layer, and an application layer from the bottom up. The transport layer is in units of data packets, including packet transmission and packet parsing. The data packet is transmitted based on ASCII characters. The format is shown in Figure 2. The fields are defined as follows.
Figure 2 Dual processor communication protocol packet format
Start byte: the starting character, defined as the character "#";
Packet type: The data type of the packet transmission, "C" indicates that the packet is transmitted as a command, "D" indicates data, and "S" indicates status.
Packet length: The length of the packet data, which defines that each packet can transmit up to 255 bytes.
Direction: the direction in which the packet is transmitted, the character "0" indicates that the command or data is transmitted from the TV to the DVB, and the character "1" indicates that the state or data is transmitted from the DVB to the TV;
CRC: Simple CRC-8 error correction code to ensure the reliability of data transmission;
End byte: The terminating character, defined as ASCII code 0x0AH (carriage return).
The Data block field is the data block of the packet. According to the data type of the transmission determined by the Packet type, the content has different conventions for the installation command, status, and data as needed.
3.3 Software Structure
The HDTV module is divided into two states: ATV and DTV. When the HDTV module is in the ATV state, the DVB module is turned off, leaving only the HDTV module to work, and the whole machine only implements the functions of the ordinary TV. When the HDTV module is in the DTV state, the DVB module is turned on, and the system is in a dual processor cooperative working state. The audio and video signals output by the DVB module are transmitted to the HDTV module through the HDMI interface.
Figure 3 software system structure of dual processor working together
The system uses only one remote control, and the remote control key code is multiplexed by two modules in different states of ATV and DTV. The remote control command is responded by the HDTV processor, and the HDTV analyzes the remote control command. If the remote control operation of the television itself is performed by the television, the remote control operation of the DVB is mapped to the command for controlling the DVB module. The packet transmission program of the communication protocol packages and transmits the command to the DVB module, and the packet parsing process of the DVB processor extracts the command content from the packet, and then the processor performs the specified action and returns the corresponding state.
The system only maintains an OSD system on the HDTV processor. When the HDTV needs to display DVB data in the DTV state, the display data is requested from the DVB module through the communication protocol, and the DVB module will need to display the data of the OSD through the communication protocol. For the HDTV module, the packet parsing program of the HDTV module extracts the data content and gives it to the OSD display.
Therefore, by this method, a single user interface is implemented on the HDTV module, and a single data access control is implemented on the DVB module. The software structure of the entire system can be seen in Figure 3.
4 Conclusion
The dual-processor-based HD digital TV design has some new technical difficulties in hardware and software. It not only means the integration of functions, but also requires dual processors to work together to achieve a single system image. In this paper, the hardware structure of the system is given. On this basis, a method of synchronizing commands and states between two processors and exchanging data to realize single system image through serial communication is proposed. This design idea provides an idea for the development of high-definition digital TV, and also has certain reference value for other embedded system design based on multi-CPU.
references
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