The setup time (setupTIme) refers to the time when the data is stable until the rising edge of the trigger's clock signal arrives. If the setup time is not enough, the data will not be triggered into the trigger on the rising edge of this clock; hold time (hold TIme) It refers to the time when the data is stable after the rising edge of the trigger's clock signal. If the hold time is not enough, the data cannot be triggered into the trigger. Data stable transmission must meet the setup and hold time requirements.
In the design, of course, I hope that the shorter the settling time, the better, and the shorter the time, the shorter the better. That is to say, it is best that the signal arrives at the edge of the clock and is used immediately after arrival, so that the theoretical efficiency is the best. Of course, the theory is all.
Competition and adventureCauses of internal burrs in PLD
When designing a digital system using discrete components, the distributed inductance and capacitance are present when the PCB is routed, so the glitch of a few nanoseconds will be naturally filtered out, and there is no distributed inductance and capacitance inside the PLD, so in the PLD/FPGA In the design, competition and risk issues will become more prominent. This is easily understood from the point of view of an analog circuit, such as adding two capacitors to a delay chain to filter out the glitch.
Adventure phenomenon in FPGA
Signals have a certain delay when they are connected and logic cells inside the FPGA device. The size of the delay is related to the length of the connection and the number of logic cells, and is also affected by the manufacturing process, operating voltage, temperature and other conditions of the device. The high and low transitions of the signal also require a certain transition time. Due to the two factors, when the level value of the multi-channel signal changes, at the moment of signal change, the output of the combinatorial logic has a sequence, not simultaneously, and some incorrect spike signals often appear. These spike signals Called "burr". If a "glitch" appears in a combinatorial logic circuit, it means that the circuit is "adventurous." (Unlike discrete components, these burrs will be completely retained and transferred to the next stage due to the absence of parasitic capacitance inductance inside the PLD. Therefore, the glitch is particularly prominent in PLD and FPGA design.) We cannot guarantee the length of all connections. Therefore, the input signal changes at the same time at the input end, but after the internal wiring of the PLD, the time of reaching the OR gate is also different, and the burr is inevitable. In a nutshell, as long as the input signal changes at the same time, the combinatorial logic will produce glitch (through the internal trace). The design method of connecting their outputs directly to the clock input, clearing or setting the port is wrong, which can have serious consequences. So we have to check all glitch-sensitive input ports such as clock, clear and set in the design to make sure the input does not contain any spurs.
How to deal with burrs(1) Using a synchronous circuit, D flip-flop: We can reduce the occurrence of burrs by changing the design and destroying the conditions generated by the glitch. For example, in digital circuit design, the Gray code counter is often used to replace the ordinary binary counter. This is because the output of the Gray code counter has only one bit transition at a time, which eliminates the occurrence of competitive risk and avoids the occurrence of glitch. Glitch is not harmful to all inputs. For example, the D input of the D flip-flop, as long as the glitch does not appear on the rising edge of the clock and meets the data setup and hold time, it will not cause harm to the system. We can say D The D input of the trigger is not sensitive to the glitch. According to this characteristic, we should use the synchronous circuit as much as possible in the system. This is because the change of the synchronous circuit signal occurs at the clock edge. As long as the glitch does not appear at the edge of the clock and does not satisfy the data setup and hold time, it does not. It can cause harm to the system. (Because the glitch is very short, mostly a few nanoseconds, it is basically impossible to meet the data establishment and retention time)
(2) The method of using the signal, that is, using another enable signal: the above method can greatly reduce the burr, but it does not completely eliminate the glitch. Sometimes, we must manually modify the circuit to remove the glitch. We usually use the "sampling" method. In general, the risk occurs when the signal is level-shifted, that is, an adventure occurs during the set-up time of the output signal, and no glitch occurs during the hold time of the output signal. If you "sample" it during the hold time of the output signal, you can eliminate the effects of the glitch signal. Two basic sampling methods: one method is to perform a logical AND operation with a high-level pulse of a certain width during the hold time of the output signal, thereby obtaining the level value of the output signal. One disadvantage of the above method is that it must be artificially guaranteed that the sample signal must be generated at the appropriate time. Another more common method is to use the D input of the D flip-flop to be insensitive to the glitch signal during the hold time of the output signal. Inside, the output signal of the combinational logic is read by a flip-flop, which is similar to converting an asynchronous circuit into a synchronous circuit. But this will have a clock cycle delay.
During the simulation, we may also find that there is an output glitch on the external output pin of the FPGA device. However, due to the short glitch and the parasitic parameters of the PCB itself, in most cases, the glitch can be naturally routed through the PCB. Regardless of the need to add RC filter.
As mentioned earlier, excellent design schemes, such as the use of Gray code counters, synchronization circuits, etc., can greatly reduce glitches, but it does not completely eliminate glitches. Glitch is not harmful to all inputs, such as the D input of the D flip-flop, as long as the glitch does not appear on the rising edge of the clock and meets the data setup and hold times, it will not harm the system. Therefore, we can say that the D input of the D flip-flop is not sensitive to the glitch. But for the clock terminal of the D flip-flop, the set terminal and the clear terminal are all burr-sensitive inputs. Any glitch will make the system go wrong, but as long as it is handled seriously, we can minimize the damage until it is eliminated. . Below we will discuss several specific signals.
Clear and set signalClearing and setting signals requires careful consideration of them as if they were clocks, as these signals are also very sensitive to glitch. As with clocks, the best clear and set is driven directly from the device's pins. It is common to have a master reset Reset pin that feeds each flip-flop or set signal to each flip-flop in the design project. Almost all PLD devices have dedicated global clear pins and global set. If a clear or set signal must be generated from within the device, these signals should be established in accordance with the "gated clock" design guidelines to ensure that the input is glitch free.
If gate clear or gate set is used, a single pin or flip-flop acts as a clear or set source and has other signals as an address or control line. The address or control line must remain stable during the period of the clear or reset
Asynchronous input signalBy definition, asynchronous inputs are not always able to meet the setup and hold time requirements of the triggers they feed. Therefore, asynchronous inputs often latch the wrong data to the flip-flop or put the trigger into a metastable state, in which the output of the flip-flop is not recognized as l or 0. Metastability can cause serious system reliability problems if not handled properly.
The use of an additional trigger to synchronize the enable signal ensures that the setup time of the counter is not violated, thereby solving the reliability problem. Although the sync flip-flop still feels metastable, it is stable until the next clock edge. In general, to avoid metastability problems in EPLDs, an asynchronous signal must never be output to two or more flip-flops in the device. Another way to synchronize asynchronous input is shown in Figure 4.2.16. The input drives the clock of a flip-flop whose data input is connected to Vcc. This circuit is useful for detecting asynchronous events that are shorter than one clock cycle.
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