Design principle of SCA architecture based on ZedBoard

Abstract : ZedBoard is Xilinx's first fully programmable system-on-chip that combines ARM Cortex A9 dual-core and 7 series FPGAs. It has the advantages of both ARM and FPGA, and is one of the best embedded platforms for miniaturized SCA. This article introduces the hardware structure of the ZedBoard platform, and aims at the problem that the SCA architecture cannot be realized on the dedicated hardware platform. Through analysis and research of the MHAL hardware abstraction layer technology and OCP interface specifications, the MHAL hardware abstract interface and FPGA that meet the ZedBoard platform hardware environment are designed. The waveform component container effectively solves the implementation problem of the SCA architecture on the ZedBoard platform, and lays the foundation for the development of the system with the SCA architecture as the core on the ZedBoard.

0 Preface

Software Communication Architecture (Software CommunicaTIons Architecure, SCA) is a software radio implementation framework proposed by the US military in the Joint TaTIcal Radio System (JTRS) for the GPP environment, combined with JTRS's subsequent introduction of SCA supplementary standards to tailor the SCA architecture. It can build a miniaturized SCA architecture on an embedded hardware platform with limited hardware resources and enhance the reusability and portability of system software. It is one of the main architectures for implementing embedded reconfigurable systems. ZedBoard is Xilinx's first embedded development environment that integrates GPP and FPGA, which can meet the needs of most embedded system development. It is an inevitable development trend of embedded development environments. However, due to the specific application components in FPGA The logic circuit implementation is completely different from the program call execution on GPP, so the SCA architecture will have many implementation problems on the ZedBoard platform [1].

This article first introduces the hardware structure of the ZedBoard platform, proposes the overall design of the SCA architecture based on ZedBoard, and focuses on the problems that the SCA architecture is difficult to implement on the ZedBoard platform. Through in-depth analysis, the Modem Hardware Abstraction Layer (MHAL) is studied The standard and Open Core Protocol (OCP) interface protocol, combined with the ZedBoard hardware structure, designed the external abstract interface of the MHAL hardware platform and the SCA waveform component container, which effectively solved the implementation problem of the SCA architecture on the ZedBoard. To implement the SCA architecture on the ZedBoard Laid the foundation for the core system development.

1 Overall design of SCA architecture based on ZedBoard

The ZedBoard platform is Xilinx ’s first fully programmable system-on-chip that integrates ARM Cortex A9 dual-core and FPGA, and combines the features and advantages of GPP and FPGA. The core of the ZedBoard platform is Xilinx's Zynq-7020 chip, which mainly includes two parts: processing system (PS) and programmable logic (PL). The PS part contains a dual-core ARM Cortex A9 processor, which is not only responsible for the management and configuration of the entire ZedBoard development board, but also can be used as an independent chip. It is the system control core of the ZedBoard platform, and also integrates the SIMD multimedia processing engine (NEON ), Memory manager (MMU) and other functional modules and a variety of external expansion interfaces, with strong functional expansion capabilities. The PL part mainly includes Xilinx's high-performance 7-series FPGA, which provides abundant IO resources and high-speed digital processing capabilities as a complement to the PS part [2-3].

The overall design of the SCA architecture based on ZedBoard is shown in Figure 1. In order to give full play to the high-performance system control capability of the PS part of the ZedBoard platform, the core framework, middleware and operating system of the SCA architecture are designed to be implemented on the ARM of the PS part; and PL Part of the high-speed digital processing capabilities and reconfigurable features are very suitable for the realization of SCA application layer waveform components. This paper solves the implementation problem of SCA architecture on FPGA through the MHAL hardware abstract interface and OCP waveform component container designed by ourselves, and uses the APC interface and IO bus of the ZedBoard platform to realize the message transmission between the core framework of the PS part and the FPGA waveform component. The following focuses on the MHAL hardware abstract interface and FPGA waveform component container.

2 MHAL hardware abstract interface design

Modem hardware abstraction layer MHAL is an interface standard promulgated by the JTRS office in 2007. Its original intention is to provide standard protocols and interfaces for the communication of different processing units in the SCA system. It also involves the abstraction of the external interface of the hardware platform to achieve SCA messages. The standard transmission on ZedBoard provides a method [4-5]. This article analyzes and studies the MHAL standard in depth, and combines the ZedBoard development environment to modify the MHAL message structure, redefines the functional structure and interface functions of the MHAL hardware abstract interface, and designs the MHAL message sending and receiving structures for ARM and FPGA, respectively. Completed the design of MHAL hardware abstract interface.

2.1 MHAL message structure design MHAL messages are arranged from the least significant bit to the most significant bit in an increasing manner of address. In this paper, the message structure in the MHAL standard is modified and expanded, and the message start character and message type field are added to make it It can better meet the implementation needs of the SCA architecture on ZedBoard. Its message structure is shown in Figure 2. The other fields are the same as the message structure in the MHAL standard, and will not be repeated here.

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