While the Cortex-M processor family targets the lower end of the performance spectrum, Cortex-M is still quite powerful compared to other typical processors used in most microcontrollers (MCUs). For example, the Cortex-M4 and Cortex-M7 processors used in many high-performance microcontrollers have a maximum clock frequency of up to 400MHz.
Of course, performance is not the only factor in choosing a processor. In many applications, low power consumption and cost are the most important criteria for customers. Therefore, the Cortex-M processor family incorporates various types of products to meet different needs (Table 1).
The difference between Cortex-M and traditional ARM processors (like ARM7TDMI, ARM9) is the greatly modified architecture. for example:
· Only ARM Thumb instructions are supported, but in Thumb-2, it has been extended to support 16-bit and 32-bit instructions.· Interrupt processing task, the built-in controller (NVIC) called by nested vector interrupt controller executes, the NVIC provides automatic priority scheduling, interrupt masks and nested configuration, and a system exception.
The interrupt handler (Handler) can be written into a regular C language function and a vectorized interrupt processing mechanism, without using software to determine which interrupt of the service. Interrupted responses are decisive and have low latency characteristics.
In terms of the interrupt vector table, the branch instruction is changed to the start address of the interrupt and the system exception handler.
Some details of the scratchpad block and the program development mode have also changed.
These changes mean that many of the combined language code written for traditional ARM processors must be modified, and the old Projects files must be modified and recompiled when ported to Cortex-M.
Instruction set overview
In most cases, the software's code is written in C or other high-level languages. However, a basic understanding of the instruction set supported by the Cortex-M processor can help determine which Cortex-M processor is required for a particular task. The Instruction Set Architecture (ISA) is part of the processor architecture and the Cortex-M processor can be divided into several architecture types (Table 2).
All Cortex-M processors support an instruction set called Thumb. After the release of Thumb-2 technology, the entire Thumb instruction set became quite large. However, different Cortex-M processors support the sub-sets of instructions in the Thumb ISA, as shown in Figure 1.
Figure 1 Instruction set supported by various Cortex-M processors
The Cortex-M0/M0+/M1 processor is based on the ARMv6-M architecture and has a very small instruction set with only 56 instructions, most of which are 16 bits, as shown in Figure 1 for the smaller ellipse. However, the scratchpad in the processor and the processed data are still 32 bits. For most simple I/O control jobs and for generating data processing, such a small instruction set is sufficient. Since the instruction set is small, only a small number of logic gates are required to build the processor. For example, the Cortex-M0 and Cortex-M0+ processors require only 12,000 logic gates. However, some of these instructions cannot be used with high-order registers (R8 to R12), and their ability to generate data on the fly is quite limited. This is primarily to make a compromise between ultra low power processor design and performance.
The Cortex-M3 processor is based on the ARMv7-M architecture and supports a large number of instruction sets, many of which are 32-bit instructions, allowing the system to use the high-order registers more efficiently. In addition, it supports vector table branch instructions and conditional execution (using IT instructions), hardware divide instructions, multiply-accumulate (MAC) operations, and variable bit field operations.
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