At present, Vivado HLS is unique in the field of High Level Synthesis (HLS). It effectively closes the distance between software engineers and FPGAs, accelerates the process of algorithm development, and shortens time to market. It is a boon for engineers, especially software engineers. In practical engineering, how to make good use of this tool is still worth studying. This article describes several misunderstandings when using Vivado HLS.
Misunderstanding 1
As long as the algorithm described in C or C++ is synthesizable (convertible to RTL).
The synthesizable functionality of HLS is limited, and not all C or C++ statements can be converted to the corresponding RTL code. The following situations are not synthesizable. 1. Dynamic memory allocation 2. Operation involving operating system level 3. Recursive function 4. Variable array size
Misunderstanding 2
Since Vivado HLS supports C, C++, and System C, you can use either of them.
Although Vivado HLS supports C, C++, and System C, the strength of support is different. The following description is given on page 56 of v2017.4 version ug871. It can be seen that when using any precision data type in the design, C++ and System C can use the debugging environment of Vivado HLS, but the algorithm described by C is not. In fact, many real hardware models use any progress data type, so to use the debugging features of Vivado HLS, it is recommended to use C++ and System.
Misunderstanding 3
As long as the source code is available, there is no Test bench.
In the HLS design and development, C Test bench plays a pivotal role. It is necessary to verify the function of the C-level algorithm; it is also used in the co-simulation of C and RTL when generating RTL code. As shown below. In fact, when co-simulation, the input incentive for RTL code is generated by C Test bench. As you can see, the C Test bench is an integral part of the overall design.
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